Many modern communication protocols transmit multiple data words in a "frame" of information. The frame includes a framing pattern, which is a predetermined combination of bits indicating the start of a frame. The frame pattern is followed by header information and data. Protocols which use this general data structure include SONET, DMI and ISDN.
Importantly, the framing information defines the beginning of a frame, such that the header information and data may be converted into the correctly aligned words. Modern communication systems necessarily use multiple device technologies to demultiplex high-speed digital signals. In order to perform serial-to-parallel conversion, high-speed technologies are used. High-speed technologies, however, are expensive and require a high power consumption.
Since the serial-to-parallel conversion process must be aligned to the frame pattern in order to correctly demultiplex the information contained in each frame, the circuitry for detecting the imbedded frame alignment pattern is also performed in the high-speed circuitry. This has two undesirable consequences. The frame pattern detector, control logic and timing generator must be implemented in the high-speed circuitry which is expensive and consumes significant power. Further, the serial-to-parallel convertor is dependent upon the pattern detection and control circuitry, thereby increasing the circuitry in the data path. The extra circuitry limits the maximum bit rate at which the system will operate. Also, since many of the other demultiplexing functions are performed in low-speed circuitry, signals must pass between the high-speed and low-speed devices to report, for example, loss of frame conditions and frame control signals.
Therefore, a need has arisen in the industry to provide a communication system wherein frame alignment may be performed in low-speed circuitry.